1. Field of the Invention
The present invention relates to a method for controlling a power relay of a microwave oven, and particularly to an improved method for controlling a power relay of a microwave oven which is capable of preventing damage of a power relay contact point and extending the life span of the relay.
2. Description of the Conventional Art
FIG. 1 shows a conventional power relay On/Off control apparatus for a microwave oven, which includes a power unit 10 for supplying power to connected elements, a microcomputer 1 for controlling the operation of the microwave oven in accordance with control signals inputted thereto, a reset unit 2 for initializing the microwave oven upon the initial application of power, a 50 Hz/60 Hz clock input unit 3 for supplying a clock signal having a frequency of 50 Hz/60 Hz to the microcomputer 1, a buzzer controller 4 for generating an alarm signal by outputting a control signal to the microcomputer 1 when the microwave oven is not operational, a door detector 5 for detecting whether the door of the microwave oven is open or closed, a power relay controller 6 for switching the power to a high voltage transformer in accordance with the control of the microwave oven 1 and for adjusting the output of a magnetos, a display controller 7 for displaying the operation state of the microwave oven in accordance with the control of the microcomputer 1, a key input detector 8 for detecting the state of a selection key which a user presses for selecting one among various kinds of cooking modes, and a main relay controller 9 for driving a load in accordance with the control of the microcomputer 1.
As shown in FIG. 2, the microcomputer 1 includes a central processing unit (CPU) 11 for performing various control operations in accordance with input signals inputted thereto, a 50 Hz/60 Hz clock input detector 12 for detecting the clock signal of 50 Hz/60 Hz, which is inputted thereto from the clock input unit 3, in accordance with the control of the CPU 11 and for outputting a detection signal, a power relay On/Off controller 18 for outputting a relay driving signal to the power relay controller 6 in accordance with the detection state of the 50 Hz/60 Hz clock input detector 12 and for deciding whether or not to open or close the contact point of the power relay of the power relay controller 6 during the "+" cycle or the "-" cycle of the power voltage, a relay on/off signal generator 14 for generating a relay on/off signal in accordance with the control signal outputted from the CPU 11, a common controller 13 for controlling the operation of the relay on/off signal generator 14 in accordance with the output signals of the 50 Hz/60 Hz clock input detector 12 and the CPU(11), an inner register 15 for storing data outputted from the CPU 11, a random access memory (RAM) 16, and a read only memory (ROM) 17.
The power relay on/off controller 18, as shown in FIG. 3, includes a 50 Hz/60 Hz clock generator 18a for generating a clock signal having a frequency of 50 Hz/60 Hz in accordance with the control of the CPU 11, an inverter I1 for inverting the output signal from the 50 Hz/60 Hz clock generator 18a, an inverter I2 for inverting the output signal from the relay on/off signal generator 14 of the microcomputer 1, an AND-gate A1 for ANDing the output signals of the inverter I1 and the inverter I2, a pulse generator 18b for generating a pulse signal in accordance with the output signal of the relay on/off signal generator 14 of the microcomputer 1, an AND-gate A2 for ANDing the output signal of the pulse generator 18b and the output signal of the inverter I1, an AND-gate A3 for ANDing the output signals of the pulse generator 18b and the 50 Hz/60 Hz clock generator 18a, an AND-gate A4 for ANDing the output signals of the inverter I1 and the 50 Hz/60 Hz clock generator 18a, a pulse generator 18c for generating a pulse signal in accordance with the output signal of the AND-gate A1, a flip-flop 18d for controlling opening/closing of the contact point of the relay during the "+" or "-" cycle of the power voltage, an AND-gate A5 for ANDing the output signal of the /Q output terminal of the flip-flop 18d and the output signal of the pulse generator 18c, an AND-gate A6 for ANDing the output signal of the /Q output terminal of the flip-flop 18d and the output signal of the AND-gate A2 and for applying the ANDed signal to the clock input of the flip-flop 18d, an AND-gate A7 for ANDing the signal of the Q output terminal of the flip-flop 18d and the output signal of the AND-gate A3, a pulse generator 18e for generating a pulse signal in accordance with the output signal of the AND-gate A4, an AND-gate A8 for ANDing the output signal of the pulse generator 18e and the signal of the Q output terminal of the flip-flop 18d, a relay off controller 18f for outputting a clock signal R in accordance with the output signals of the AND-gates A5 and A8, a relay On controller 18g for outputting a clock signal S in accordance with the output signals of the AND-gates A6 and A7, and a relay driving apparatus for receiving the output signals R and S from the relay On controller 18g and the relay Off controller 18f and for outputting the relay driving signal to the power relay controller 6.
The operation of the power relay of/off controller for a conventional microwave oven will now be explained with reference to the accompanying drawings.
The clock signal of 50 Hz/60 Hz outputted from the 50 Hz/60 Hz clock input unit 3 is inputted into the 50 Hz/60 Hz clock input detector 12 of the microcomputer 1, and the 50 Hz/60 Hz clock input detector 12 detects the state of the 50 Hz/60 Hz clock in accordance with the control of the CPU 11, and applies the detected signal to the 50 Hz/60 Hz clock generator 18a of the power relay on/off controller 18.
In step ST1, the CPU 11 of the microcomputer 1 judges whether the 50 Hz/60 Hz clock signal is outputted from the 50 Hz/60 Hz clock generator 18a during the "+" or "-" cycle of the power voltage, and in step ST2, when the 50 Hz/60 Hz clock signal is outputted during the "+" cycle, it is judged whether a relay on flag stored in the RAM 16 is set. Here, the relay on flag is a predetermined data indicating whether the power relay is turned on or off.
As a result of the judgement, if the relay on flag is set, the CPU 11 judges whether the "+" cycle on flag is set in step ST3, and if the "+" cycle on flag is set, step ST4 is performed. Here, the "+" cycle on flag is stored in the RAM 16, and refers to the data indicating whether the power relay is on during the "+" or "-" cycle of the power voltage.
Namely, in step ST4, the relay on/off signal generator 14 outputs a high level signal in accordance with the control of the CPU 11, and controls the 50 Hz/60 Hz clock generator 18a to output a high level signal.
When the output of the 50 Hz/60 Hz clock generator is a high level, the AND-gates A1, A2, A5 and A6 output a low level signal, and the AND-gates A3 and A7 output a high level signal.
Therefore, the relay off/on control apparatuses 18f and 18g output control signals, respectively, and the relay driving apparatus 18h applies the relay driving signal to the power relay controller 6, and turns on the power relay.
The CPU 11 resets the "+" cycle on flag, and finishes the control process.
Meanwhile, if it is judged that the relay on flag is not set in step ST2, the CPU 11 judges whether the "+" cycle on flag is set in step ST5. As a result, if it is set, step ST6 is performed.
Namely, in step ST6, the relay on/off signal generator 14 outputs a low/high level signal in accordance with the control of the CPU 11. When the clock signal outputted from the 50 Hz/60 Hz clock generator 18a is a high level, the AND-gate A4 outputs a high level signal to the clock generator 18e, and the pulse generator 18e outputs a high level signal to the AND-gate A8.
The relay off/on controllers 18f and 18g output the control signals, respectively, and the relay driving apparatus 18h applies the relay driving signal to the power relay controller 6, and turns off the power relay.
Meanwhile, if the output signal from the 50 Hz/60 Hz clock generator 18a is a low level in step ST1, in step ST7, the CPU 11 judges whether the relay on flag is set. When the relay on flag is set, the CPU 11 performs step ST8.
Namely, in step ST8, it is judged whether the "+" cycle on flag is set. If it is set, the control process is finished. If it is not set, the 50 Hz/60 Hz clock generator 18a is enabled to output a low level signal. At this time, the on/off signal generator 14 outputs a high level signal.
In case that the output signal from the 50 Hz/60 Hz clock generator 18a is a low level, the AND-gates A3, A4, A7, and A8 output a low level signal, respectively, and the AND-gates A1, A2, and A6 output a high level signal, respectively.
Thereafter, as was described for step ST1, the power relay is turned on, and the CPU 11 sets the "+" cycle on flag.
If it is judged in step ST7 that the relay on flag is not set, the CPU (11) judges whether the "+" cycle on flag is set in step ST9. As a result, it is set, the control process is finished. If the "+" cycle on flag is not set, the relay on/off signal generator 14 outputs a low level signal in accordance with the control of the CPU 11, and a pulse signal is applied to the input of the AND-gate A5.
At this time, when the signal outputted through the Q output terminal Q of the flip-flop 18d is a high level, the relay off controller 18f is operated, and the power relay is turned off in accordance with the process of step ST6.
However, in the above-described conventional art, when the relay contact point of the power relay is opened at a predetermined point "A" (or "A'"), a spark is generated during the time from the point "A" (or "A'") to the point "C" (or "C'") even when the relay point is opened at the point "A" (or "A'"), and the current flows therethrough.
Since the spark generation time is lengthy, and a lot of current flows therein, the relay contact point may be damaged, and the life span of the relay is shortened.